1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a dynamic type semiconductor memory device which is accessible at a high speed.
2. Description of the Background Art
FIG. 97 schematically illustrates the structure of a main part of a conventional semiconductor memory device. Referring to FIG. 97, the semiconductor memory device includes a plurality of array blocks MBa to MBn. Each of the array blocks MBa includes a plurality of memory cells MC arranged in a form of rows and columns, a plurality of word lines WL arranged in correspondence to the respective rows and connected with the memory cells of the corresponding rows, and a plurality of bit line pairs BLP arranged in correspondence to the respective columns and connected with the memory cells of the corresponding columns. FIG. 97 representatively illustrates a single word line WL and a single bit line pair BLP in each of the array blocks MBa to MBn.
X decoders XDa to XDn, sense amplifier bands SABa to SABn and selector bands STRa to STRn are arranged in correspondence to the array blocks MBa to MBn respectively, while a Y decoder YD and a global I/O bus GI/O are provided in common for the array blocks MBa to MBn.
The X decoders XDa to XDn decode supplied row address signals (paths therefor are not shown in FIG. 97) upon activation thereof, to drive word lines which are arranged in correspondence to addressed rows of the corresponding array blocks MBa to MBn respectively.
The sense amplifier bands SABa to SABn include sense amplifiers which are arranged in correspondence to the respective columns (the bit line pairs BLP) of the corresponding array blocks MBa to MBn respectively, and detect, amplify and latch memory cell data appearing on the corresponding bit line pairs BLP upon activation thereof.
The Y decoder YD decodes supplied column address signals, and transmits a column selection signal for selecting an addressed column onto a column selection line CS. The selector bands STRa to STRn connect the addressed column (the bit line pairs BLP) which is designated by an array block selection signal (not shown) to the global I/O bus GI/O in response to the column selection signal transmitted from the Y decoder YD onto the column selection signal line CS and to the array block selection signal.
The global I/O bus GI/O is provided with a read driver RDR which is activated in data reading for amplifying data on the global I/O bus GI/O for transmission onto an internal read/write bus RWBS, and a write driver WDR which is activated in data writing for buffering data on the internal read/write bus RWBS for transmission to the global I/O bus GI/O.
An output buffer OBF which is activated in data reading for buffering the data on the internal read/write bus RWBS for outputting to a data input/output terminal DQ, and an input buffer IBF which is activated in data writing for forming internal write data from a data signal received from the data input/output terminal DQ for transmission to the internal read/write bus RWBS are provided between the read/write bus RWBS and the data input/output terminal DQ.
In the semiconductor memory device shown in FIG. 97, only one of the plurality of array blocks MBa to MBn is activated. In a state referred to as "array activation", a word line is selected in an array so that data of a memory cell which is connected with the selected word line is read onto each bit line pair BLP and amplified by an associated sense amplifier. Data is written in/read from only an array block which is designated by an array block selection signal.
FIG. 98 illustrates the internal structure of each of the array blocks MBa to MBn shown in FIG. 97 in detail. This FIG. 98 representatively shows only the structure of a portion which is related to one column of a single array block, with only a single word line WL shown.
Referring to FIG. 98, the bit line pair BLP includes bit lines BL and ZBL transmitting data signals which are complementary to each other. A memory cell MC which is arranged at the crossing between the bit line BL and the word line WL includes a capacitor MQ storing data in the form of electric charges, and an access transistor MT formed by an n-channel MOS transistor and connecting the memory capacitor MQ to the bit line BL in response to a signal potential on the word line WL.
A sense amplifier SA included in the sense amplifier band SAB includes a p-channel MOS transistor P1 having a first conduction terminal connected with the bit line BL, a control gate connected with the bit line ZBL, and a second conduction terminal coupled to receive a sense amplifier activation signal Vp, a p-channel MOS transistor P2 having a first conduction terminal connected with the bit line ZBL, a control gate connected with the bit line BL, and a second conduction terminal coupled to receive the sense amplifier activation signal Vp, an n-channel MOS transistor N4 having a first conduction terminal connected with the bit line BL, a control gate connected with the bit line ZBL, and a second conduction terminal coupled to receive a sense amplifier activation signal Vn, and an n-channel MOS transistor N5 having a first conduction terminal connected with the bit line ZBL, a control gate connected with the bit line BL, and a second conduction terminal coupled to receive the sense amplifier activation signal Vn.
The p-channel MOS transistors Pl and P2 form a flip-flop, to drive one having a higher potential of the bit lines BL and ZBL to a high level upon activation (high level) of the sense amplifier signal Vp. The n-channel MOS transistors N4 and N5 also form a flip-flop, to drive one having a lower potential of the bit lines BL and ZBL to a low level upon activation (low level) of the sense amplifier activation signal Vn.
A local I/O bus LI/OA consisting of local I/O lines LIOa and LIOb is arranged for an array block MB#A (any of MBa to MBn).
The selector band STR includes a column selection gate CSEL provided for the bit lines BL and ZBL to connect these bit lines BL and ZBL to the local I/O lines LIOa and LIOb in response to a column selection signal CS (a signal which is transmitted onto the column selection signal line shown in FIG. 97 and denoted by the same symbol), and a block selection gate BSELA for connecting the local I/O lines LIOa and LIOb respectively to global I/O lines GIOa and GIOb forming the global I/O bus GI/O in response to an array block selection signal TGA. The column selection gate CSEL includes a transfer gate N6 formed by an n-channel MOS transistor arranged between the bit line BL and the local I/O line LIOa, and a transfer gate N7 formed by an n-channel MOS transistor arranged between the bit line ZBL and the local I/O line LIOb. The block selection gate BSELA includes a transfer gate N8 formed by an n-channel transistor arranged between the local I/O line LIOa and the global I/O line GIOa, and a transfer gate N9 formed by an n-channel MOS transistor arranged between the local I/O line LIOb and the global I/O line GIOb.
FIG. 98 also shows a block selection gate BSELB which is provided for another array block MB#B. This block selection gate BSELB connects a local I/O line arranged for this array block MB#B to the global I/O bus GI/O in response to a block selection signal TGB.
The read driver RDR differentially amplifies complementary signals appearing on the global I/O bus GI/O, for transmission to the internal read/write bus RWBS. The write bus driver WDR amplifies the signals on the internal read/write bus RWBS, forms complementary write data, and transmits the amplified onto the global I/O lines GIOa and GIOb.
The bit lines BL and ZBL are provided with an equalize/precharge circuit EP which in turn precharges and equalizes the bit lines BL and ZBL at a prescribed precharge potential Vpr in response to an equalization signal EQ. This equalize/precharge circuit EP includes an n-channel MOS transistor Ni for connecting the bit lines BL and ZBL with each other in response to the equalization signal EQ, an n-channel MOS transistor N2 for transmitting the precharge potential Vpr to the bit line BL in response to the equalization signal EQ, and an n-channel MOS transistor N3 for transmitting the precharge potential Vpr to the bit lines ZBL in response to the equalization signal EQ. The equalization signal EQ enters a high level of an active state in a standby cycle of this semiconductor memory device. Operations are now described.
Consider an operation of replacing certain pixel data with another pixel data, which operation is frequently performed in image picture data processing or the like.
Such an operation is executed in picture duplication processing or the like. An operation of transferring pixel data from the array block MB#A to the other array block MB#B will be described with reference to FIG. 99, which in turn is an operation waveform diagram. Referring to FIG. 99, control signals and the local I/O bus which are related to the array block MB#A are shown with ending characters "A", while those related to the array block MB#B are shown with ending characters "B".
When a row address strobe signal ZRAS is in an inactive state of a high level, both of equalization signals EQA and EQB are at high levels of active states. When the address strobe signal ZRAS is brought into an active state of a low level, a memory cell selecting operation in this semiconductor memory device is started. An externally supplied address signal (not shown) designates the array block MB#A, whereby the equalization signal EQA for this array block MB#A is brought to a low level and the equalize/precharge circuit EP is inactivated. Thus, the bit lines BL and ZBL are brought into floating states at the precharge potential Vpr in the array block MB#A. Then, a word line WLA is selected in the array block MB#A by the X decoder shown in FIG. 54 in accordance with an address signal which is supplied at the falling edge of the row address strobe signal ZRAS, and the potential on the word line WLA is increased. Thus, data of a memory cell which is connected with the selected word line WLA is read on a bit line pair BLPA, and the potentials of the bit line pair BLPA are changed in accordance with the selected memory cell data. FIG. 99 shows a waveform in the case of reading high-level data, as an example.
Then, when a prescribed time elapses and the potential difference between bit lines BLA and ZBLA of the bit line pair BLPA is sufficiently increased, the sense amplifier activation signals Vp and Vn are activated, so that the sense amplifier SA which is included in a sense amplifier band SABA differentially amplifies the potential difference on the bit line pair BLPA.
After the potential difference between the bit lines BL and ZBL is sufficiently enlarged by the sense amplifier SA, a column selection signal CSA from the Y decoder YD rises to a high level indicating a selecting state and the column selection gate CSEL conducts so that the bit lines BL and ZBL are connected to the local I/O lines LIOa and LIOb.
Then, the block selection signal TGA from a block decoder (not shown) is brought to a high level indicating a selecting state and the block selection gate BSELA conducts, so that the local I/O lines LIOa and LIOb are connected to the global I/O lines GIOa and GIOb. Thus, data of the selected memory cell detected and amplified by the sense amplifier SA is transmitted onto the global I/O bus GI/O.
Thereafter the read driver RDR is activated to differentially amplify the signal supplied on the global I/O bus GIto, forms internal read data and transmits the same onto the internal read/write bus RWBS. The internal read data on the internal read/write bus RWBS is transmitted to the data input/output terminal DQ through the output buffer OBF (see FIG. 97). The read data is temporarily stored in data holding means such as a register provided in an exterior, to be rewritten in another array block of the semiconductor memory device. The semiconductor memory device performs an array precharge operation, in order to select another word line. Namely, the row address strobe signal ZRAS enters a high is level of an inactive state, the selected word line WLA of the selected array block MB#A is brought into a non-selected state, and the access transistor MT included in the memory cell MC is brought into a nonconducting state.
Thereafter the sense amplifier activation signals Vp and Vn are inactivated and then the equalization signal EQA goes to a high level for activating the equalize/precharge circuit EP, thereby precharging the bit lines BL and ZBL of the bit line pair BLPA at the intermediate potential Vpr. At this time, the column selection signal CSA is in a nonselected state at a low level, and the bit line pair BLPA and the local I/O bus LI/OA are isolated from each other, while the local I/O bus LI/OA and the global I/O bus GI/O are also isolated from each other. Further, the output buffer OBF for the data input/output terminal DQ is inactivated and brought into an output high impedance state.
Then, the row address strobe signal ZRAS is brought into a low level of an active state again, in order to select the array block MB#B. At the same time, an address signal is supplied to designate the array block MB#B and a word line WLB in the array block MB#B. Thus, an equalization signal EQB enters a low level and an equalize/precharge circuit EP is inactivated in the designated array block MB#B. After the selected memory cell data appears on a bit line pair BLPB, sense amplifier activation signals VpB and VnP are activated so that the potentials of the bit line pair BLPB are changed in accordance with the selected memory cell data. Then, a column selection signal CSB enters a high level, so that the bit line pair BLPB is connected to a local I/O bus LI/OB. On the other hand, the data which is previously read and temporarily held externally is written through the input buffer IBF for data writing, and the written data is transmitted onto the global I/O bus through the write driver WDR.
When the data is transmitted onto the global I/O bus, the array block selection signal TGB enters a high level and the block selection gate BSELB conducts so that the global I/O bus GI/O and the local I/O bus LI/OB are connected with each other and the write data is transmitted to the local I/O bus LI/OB, and then to the selected bit line pair BLPB through a column selection gate CSELB. Driving ability of the write driver WDR is larger than the latching ability of the sense amplifier SA, whereby latch data of the sense amplifier SA provided for the bit line pair BLPB changes to the write data.
When the write operation is completed, the row address strobe signal ZRAS is brought into an inactive state at a high level again, the selected word line in the array block MB#B is inactivated again, the sense amplifier activation signals VpB and VnB are inactivated, a selector band STRB is also brought into a nonconducting state, and the local I/O bus LI/OB and the global I/O bus GI/O are isolated from each other. Thus, the array block MB#B is brought into a precharged state.
In the semiconductor memory device of an array division partial activation structure in which the memory array us divided into a plurality of array blocks and only one array block is activated, two ZRAS cycles (cycles as to the row address strobe signal ZRAS) are necessary for transferring data of a memory cell of an array block to a memory cell of another array block. In other words, a cycle of selecting a memory cell of a first array block and reading the data of the selected memory cell to an exterior of the device and a cycle of selecting a memory cell of a second array block and writing the externally read data in the selected memory cell are required. Thus, the data cannot be transferred between the array blocks at a high speed. Particularly when this semiconductor memory device is employed for image processing, an image processing such as duplication cannot be performed at a high speed but the data processing speed (drawing speed) is reduced and the performance of the processing system is deteriorated.
Further, bit lines are charged and discharged twice in total in the first and second array blocks in the data transfer. The bit lines are charged and discharged through the signal lines transmitting the sense amplifier activation signals vp and Vn. Thus, current consumption for driving the sense amplifiers is disadvantageously increased.
When the access designation is changed from an array block to another one in a semiconductor memory device of a divided array structure, it is necessary to temporarily drive the semiconductor memory device to a precharged state (nonselected state), since the array blocks cannot be driven independently of each other. Therefore, a time called a RAS precharge time is required at the minimum in such change of the array blocks, and hence the access time is lengthened and rapid access cannot be performed.
When a single array block is accessed in a page mode, it is necessary to temporarily drive a selected page (selected word line) to a nonselected state and then drive the next page (word line) to a selected state in page switching (switching of the selected word line). Also in this case, the time called a RAS precharge time is required at the minimum, and hence the page cannot be switched at a high speed, and rapid access cannot be obtained.
In the conventional semiconductor memory device, further, connection between an internal data bus, i.e., input/output buffers, and bus lines of external data bus is fixedly set in one-to-one correspondence. A certain type of CPU (central processing unit) is provided with a byte swap function, so that 8-bit memories storing 8-bit data and the 8-bit data can be utilized in a 16-bit processing system by performing data transfer through upper or lower 8-bit data bus among 16-bit data bus, for example. In this byte swap function, however, connection between the CPU bus and memory bus is simply switched between upper and lower byte buses, while the switching mode is fixedly set for each memory. For example, a single 8-bit memory is connected with only upper or lower 8-bit bus of the CPU bus. For example, the CPU bus utilized in data writing and reading of this 8-bit memory cannot be changed, 8-bit data read from the 8-bit memory cannot be selectively connected to the upper or lower bus of the CPU bus depending on the processing application, and hence the data cannot be properly stored in internal registers of the CPU according to the contents of the arithmetic processing, the CPU changes the positions for storing the 8-bit data according to the arithmetic processing contents again in its interior, and the processing operations of the CPU are disadvantageously complicated.
When data transfer is performed through the byte swap function, unused data bus are in free states, disadvantageously leading to low bus utilization efficiency.